1. The Field of the Invention
The present invention relates to semiconductor chip processing. More particularly, the present invention relates to formation of interlayer dielectrics that cover electrically conductive interconnects. In particular, the present invention relates to a method of resisting oxidation from the top surface of an electrically conductive interconnect during the formation of an interlayer dielectric.
2. The Relevant Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which includes active or operable portions of semiconductor devices. In the context of this document, the term xe2x80x9csemiconductive substratexe2x80x9d is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term substrate refers to any supporting structure including but not limited to the semiconductive substrates described above.
Semiconductor chip processing technology involves miniaturizing a plurality of semiconductive devices and placing them side-by-side upon a wafer. As miniaturization technology progresses, it has become expedient to stack semiconductive devices in order to retain a small chip footprint. It is also necessary to connect stacked devices by way of formation of an interconnect corridor and by filling of the interconnect corridor with electrically conductive material such as a tungsten stud. Metallization lines are formed that make electrical connection to the tungsten stud. These metallization lines need to be electrically isolated from semiconductive devices that are formed above an existing layer of semiconductive devices. To this end, an interlayer dielectric (ILD) such as an oxide or nitride is formed
FIG. 1 is an elevational cross-section view of a semiconductor structure 10 that depicts interconnects 12 within a dielectric layer 14. Semiconductor structure 10 has an upper surface 16 upon which an interlayer dielectric (ILD) layer 18 has been formed. The left half of FIG. 1 depicts an initial effect of formation of ILD layer 18 according to the prior art. It can be seen that the portion of interconnect 12 that was exposed as part of upper surface 16 of semiconductor structure 10 has formed an oxide husk 20 upon interconnect 12. Oxide husk 20 is formed either after planarization to form upper surface 16, such as by chemical-mechanical planarization (CMP) or during the deposition of ILD layer 18. Where interconnect 12 is a tungsten plug, oxide husk 20 forms into tungsten oxide (WO3).
Further processing of semiconductor structure 10, including thermal processing, causes complications that arise in the prior art. The right half of FIG. 1 depicts one prior art problem It can be seen that, due to a large stress between oxide husk 20 and interconnect 12, oxide husk 20 has delaminated from interconnect 12 due to adhesion failure, and pushed upwardly to form a void 22 immediately above interconnect 12. Void 22 causes planarity problems and can also lead to underetched trenches prior to metal fill. The delamination of oxide husk 20 is an indication of a relatively thick oxide over interconnect 12. The thickness of oxide husk can range from about 10 xc3x85 to about 500 xc3x85. Oxide husk 20 needs to be removed prior to deposition of a metal line. The presence of void 22 causes a prominence in the ILD topology. The prominence can lead to underetched trenches prior to metal fill, resulting in the metal line not making sufficient electrical contact with interconnect 12. In addition, the prominence caused by the formation of void 22 can be formed during ILD deposition. Additionally, the prominence formed due to void 22 could cause some imaging problems because of a departure from substantial planarity of the upper surface of the ILD.
The delamination of oxide husk 20 from upper surface 16 immediately above interconnect 12 creates significant yield problems and device failure both during device testing and in the field.
What is needed in the art is a method of overcoming the prior art problems. What is also needed in the art is a method of forming an ILD layer without the formation of an oxide husk and the subsequent formation of a void between the top of the interconnect and the ILD layer. What is needed in the art is a method of preventing or reducing the oxidation of the upper surface of a metallic interconnect during the formation of an interlayer dielectric.
The present invention relates to the formation of an ILD layer while preventing or reducing oxidation of the upper surface of an electrically conductive interconnect or contact. Prevention or reduction of oxidation of the upper surface of an interconnect or contact is achieved according to the present invention by passivating the exposed upper surface of the interconnect or contact prior to formation of the ILD. It is to be understood that xe2x80x9cinterconnectxe2x80x9d and xe2x80x9ccontactxe2x80x9d can be interchangeable in the inventive method and structures.
In order to avoid the oxidation of an upper surface of an interconnect during the formation of an ILD layer, an in situ passivation of the upper surface of the interconnect, immediately prior to or simultaneously with the formation of the ILD layer, avoids the problems of the prior art.
A preferred embodiment of the present invention comprises providing a semiconductor structure including a dielectric layer. Following the formation of the dielectric layer, a depression is formed in the dielectric layer. The depression terminates at an electrically conductive structure therebeneath. The depression is then filled with an interconnect that is composed of an electrically conductive material, such as a refractory metal, and preferably tungsten. After filling of the depression with the interconnect, an upper surface of the interconnect and dielectric layer is formed by a method such as chemical-mechanical planarization (CMP).
Following the formation of the upper surface, a chemical composition is reacted with at least one monolayer of the upper surface of the interconnect to form a chemical compound having a higher resistance to oxidation than the interconnect.
Preferably, the chemical composition will be a nitrogen-containing chemical compound such as ammonia, NH3. Where the interconnect is a refractory metal, such as tungsten, the at least one monolayer forms a tungsten nitride-type composition or adsorbed complex. Following formation of the at least one monolayer upon the upper surface of the interconnect, formation of the ILD layer may be carried out by such methods as a deposition by the decomposition of tetra ethyl ortho silicate (TEOS), or by chemical vapor deposition (CVD) of oxides, nitrides, carbides, and the like.
In order to form an ILD layer using lower processing temperatures, it is preferred that a CVD be carried out under plasma-enhanced (PE) conditions, i.e., PECVD.
Formation of the ILD layer may be carried out in a manner that introduces materials to form the ILD layer simultaneously with the introduction of the ammonia plasma to create a passivation layer upon the upper surface of the interconnect.
Next, formation of the ILD layer with substantially like materials is carried out under conditions where the ILD layer substantially absorbs the passivation layer and the passivation layer is sufficiently thick to resist substantial formation of the oxide husk.
Alternative compositions to ammonia may be used during plasma treatment of the upper surface of the interconnect. For example, nitrogen-containing compositions that are preferred for the inventive method include ammonia, diatomic nitrogen, nitrogen-containing silane, and the like.
These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.